Memory devices are susceptible to errors such as transient (or soft) errors. If these errors are not handled properly, they can cause a computing system to malfunction. Redundant information in the form of error correction code (ECC) bits can be used to improve overall system reliability. In some cases, additional memory devices are added to a system to support the ECC bits. In other cases, the same memory device (e.g., a dynamic random access memory (DRAM) device) can be used for both ECC and non-ECC modes.
A posted write buffer (PWB) refers to a buffer to which data is posted prior to being retired to the memory array of a memory device. In some cases, the PWB may be divided into two (or more) elements each of which may be physically located close to a corresponding portion of the memory array. In such cases, writing data to the memory array may include a two step process. First, a copy of the write data may be posted to both elements of the PWB. Subsequently, a column address strobe (CAS) is used to provide the destination address to the PWB. The copy of the write data that is posted to the element of the PWB that is closest to the appropriate part of the memory array is written into the array. This arrangement, however, does not work well if the device is capable of operating in an ECC mode.